The present invention relates in general to integrated circuit testing and, more particularly, to Joint Test Action Group (JTAG) testing of multichip modules.
Integrated circuits (IC) generally require extensive testing to ensure proper operation and functionality. To aid in the testing of ICs, JTAG procedures have developed into IEEE standard 1149.1. One of the features of JTAG testing allows for testing of interconnects between IC chips. To test interchip interconnects, JTAG uses a boundary scan technique where a continuous string of serially coupled registers are added to each IC with the output register of one IC chip coupled to the input register of the next IC chip. Each register is commonly referred to as a boundary scan cell and there is generally one boundary scan cell per each I/O pin of the IC chip.
To perform an interchip interconnect test, a test signal is applied to the first cell of the first IC chip, i.e. TEST DATA IN, and shifted along the boundary scan cells to the cell associated with the I/O pin that is to be tested for connectivity. Assuming the interconnect is intact, the test signal should propagate to another I/O pin as determined by, the particular interchip interconnect. The test signal is then captured in the JTAG cell associated with the second I/O pin and shifts along the remaining boundary scan cells to the last register of the last IC chip. If the interchip interconnect is intact then the test signal Should appear at the final JTAG output cell, i.e. TEST DATA OUT. The IEEE 1149.1 standard also has provisions for testing functionality of the IC.
A unique problem occurs for applications involving multichip modules (MCM). An MCM includes a plurality of IC die disposed on a single substrate. The MCM substrate package having multiple IC die is later integrated by end users into larger systems or circuit boards containing other IC chips, or possibly other MCMs. Thus, for testing purposes the manufacturer treats the MCM as a collection of ICs. However, the end user treats the MCM as a single IC for testing purposes even though it contains multiple IC die on its own.
One of the requirements of JTAG testing under the IEEE 1149.1 standard is to support bypass mode where an IC chip can be disabled from shifting the test pattern. Bypass mode is typically used to speed up the testing process by side stepping an IC if its particular connectivity is not under test. Consequently, there is no reason to shift the test signal through the IC if its connectivity is not under test. The IEEE standard calls for a single-register (one clock cycle) delay through the IC chip when operating in JTAG bypass mode.
The problem arises for MCMs in that the end user treats the MCM as a single IC chip although in reality it contains multiple IC die on a single substrate. Each IC die on the MCM has a single-register delay because of the need to be JTAG compatible. The multiple IC die on the MCM, each with its own single-register delay, violates the one clock cycle delay standard for the MCM as a whole when in the end user's hands. For example, assume the MCM includes six JTAG compatible IC die each with a single-register delay to comply with the IEEE standard. When the end user puts the MCM in bypass mode the test signal would undergo six register delays through the six IC die of the MCM, thereby violating the one clock cycle delay IEEE standard for the MCM as a whole.
Most if not all MCMs fail to support JTAG testing for the end user who wishes to treat the MCM as a single IC chip in the larger system. Hence, a need exists to support JTAG testing on MCMs for the end user.